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Features
* Core
- ARM(R) Cortex(R)-M3 revision 2.0 running at up to 96 MHz - Memory Protection Unit (MPU) - Thumb(R)-2 instruction set Memories - From 64 to 256 Kbytes embedded Flash, 128-bit wide access, memory accelerator, dual bank - From 16 to 48 Kbytes embedded SRAM with dual banks - 16 Kbytes ROM with embedded bootloader routines (UART, USB) and IAP routines - Static Memory Controller (SMC): SRAM, NOR, NAND support. NAND Flash controller with 4-kbyte RAM buffer and ECC System - Embedded voltage regulator for single supply operation - POR, BOD and Watchdog for safe reset - Quartz or resonator oscillators: 3 to 20 MHz main and optional low power 32.768 kHz for RTC or device clock. - High precision 8/12 MHz factory trimmed internal RC oscillator with 4 MHz Default Frequency for fast device startup - Slow Clock Internal RC oscillator as permanent clock for device clock in low power mode - One PLL for device clock and one dedicated PLL for USB 2.0 High Speed Device - Up to 19 peripheral DMA (PDC) channels and 4-channel central DMA Low Power Modes - Sleep and Backup modes, down to 2.5 A in Backup mode. - Backup domain: VDDBU pin, RTC, 32 backup registers - Ultra low power RTC: 0.6 A Peripherals - USB 2.0 Device: 480 Mbps, 4-kbyte FIFO, up to 7 bidirectional Endpoints, dedicated DMA - Up to 4 USARTs (ISO7816, IrDA(R), Flow Control, SPI, Manchester support) and one UART - Up to 2 TWI (I2C compatible), 1 SPI, 1 SSC (I2S), 1 HSMCI (SDIO/SD/MMC) - 3-Channel 16-bit Timer/Counter (TC) for capture, compare and PWM - 4-channel 16-bit PWM (PWMC) - 32-bit Real Time Timer (RTT) and RTC with calendar and alarm features - 8-channel 12-bit 1Msps ADC with differential input mode and programmable gain stage, 8-channel 10-bit ADC I/O - Up to 96 I/O lines with external interrupt capability (edge or level sensitivity), debouncing, glitch filtering and on-die Series Resistor Termination - Three 32-bit Parallel Input/Outputs (PIO) Packages - 100-lead LQFP, 14 x 14 mm, pitch 0.5 mm - 100-ball LFBGA, 9 x 9 mm, pitch 0.8 mm - 144-lead LQFP, 20 x 20 mm, pitch 0.5 mm - 144-ball LFBGA, 10 x 10 mm, pitch 0.8 mm
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AT91ARM M3 Cortex-based Processor ATSAM3U Series Preliminary Summary
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NOTE: This is a summary document. The complete document is available on the Atmel website at www.atmel.com.
6430BS-ATARM-01-Sep-09
1. SAM3U Description
Atmel's SAM3U series is a member of a family of Flash microcontrollers based on the high performance 32-bit ARM Cortex-M3 RISC processor. It operates at a maximum speed of 96 MHz and features up to 256 Kbytes of Flash and up to 52 Kbytes of SRAM. The peripheral set includes a High Speed USB Device port with embedded transceiver, a High Speed MCI for SDIO/SD/MMC, an External Bus Interface with NAND Flash controller, up to 4x USARTs (SAM3U1C/2C/4C have 3), up to 2x TWIs (SAM3U1C/2C/4C have 1), up to 5x SPIs SAM3U1C/2C/4C have 4), as well as 4x PWM timers, 3x general purpose 16-bit timers, an RTC, a 12-bit ADC and a 10-bit ADC. The SAM3U architecture is specifically designed to sustain high speed data transfers. It includes a multi-layer bus matrix as well as multiple SRAM banks, PDC and DMA channels that enable it to run tasks in parallel and maximize data throughput. It can operate from 1.62V to 3.6V and comes in 100-pin and 144-pin LQFP and BGA packages. The SAM3U device is particularly well suited for USB applications: data loggers, PC peripherals and any high speed bridge (USB to SDIO, USB to SPI, USB to External Bus Interface).
1.1
Configuration Summary
The SAM3U series differ in memory sizes, package and features list. Table 1-1 summarizes the configurations of the six devices.
Table 1-1.
Configuration Summary
Flash Organization SRAM dual plane 52 Kbytes 36 Kbytes 20 Kbytes 52 Kbytes 36 Kbytes 20 Kbytes Number of PIOs 96 Number of USARTs 4 Number of TWI 2 FWUP, SHDN pins Yes External Bus Interface 8 or 16 bits, 4 chip selects, 24-bit address 8 or 16 bits, 4 chip selects 24-bit address 8 or 16 bits, 4 chip selects, 24-bit address 8 bits, 2 chip selects, 8-bit address HSMCI data size 8 bits
Device SAM3U4E
Flash 2x 128 Kbytes 128 Kbytes 64 Kbytes 2 x 128 Kbytes 128 Kbytes 64 Kbytes
Package LQFP144 BGA144 LQFP144 BGA144 LQFP144 BGA144 LQFP100 BGA100 LQFP100 BGA100 LQFP100 BGA100
ADC 2 (8+ 8 channels) 2 (8+ 8 channels) 2 (8+ 8 channels) 2 (4+ 4 channels) 2 (4+ 4 channels) 2 (4+ 4 channels)
SAM3U2E
single plane
96
4
2
Yes
8 bits
SAM3U1E
single plane
96
4
2
Yes
8 bits
SAM3U4C
dual plane
57
3
1
No
4 bits
SAM3U2C
single plane
57
3
1
No
8 bits, 2 chip selects, 8- 4 bits bit address 8 bits 2 chip selects, 8-bit address 4 bits
SAM3U1C
single plane
57
3
1
No
Note:
1. The SRAM size takes into account the 4 Kbytes RAM buffer of the NAND Flash Controller (NFC) which can be used by the core if not used by the NFC.
2
SAM3U Series
6430BS-ATARM-01-Sep-09
Figure 2-1.
SE
L
TD TDI O TM /TR SA T/ C CK SW ES /S DIO WO W CL K
JT AG
TST
System Controller
JTAG & Serial Wire
HS UTMI Transceiver
VD
VD
MASTER
SLAVE
DI
DO
II TM P M DP DM U D G FSDFSDHS HS VD VB D D D D
N UT
6430BS-ATARM-01-Sep-09
In-Circuit Emulator SysTick Counter
2. SAM3U Block Diagram
PCK0-PCK2
Voltage Regulator
EBI
PLLA
UPLL PMC MPU I/D S
Flash Unique Identifier
USB Device HS
NAND Flash Controller & ECC
XIN XOUT
OSC 3-20 M
Cortex-M3 Processor Fmax 96MHz DMA
N V I C
NANDRDY
144-pin SAM3U4/2/1E Block Diagram
RC Osc. 12/8/4 M
WDT
5-layer AHB Bus Matrix
Nand Flash SRAM (4KBytes)
D0-D15 A0/NBS0 A1 A2-A20
VDDUTMI
SM
VDDCORE
BOD ROM 16KBytes Peripheral Bridge APB 4-Channel DMA
RC 32k RTT RTC PDC PDC PWM PDC PDC PDC
8 GPBREG
NCS0 NCS1 NRD NWR0/NWE NWR1/NBS1 NWAIT A23 A21/NANDALE A22/NANDCLE NCS3
XIN32 XOUT32
OSC 32K
FLASH 2x128KBytes 1x128 KBytes 1x 64kbytes SRAM0 32KBytes 16KBytes 8KBytes SRAM1 16KBytes 16KBytes
Peripheral DMA Controller
Static Memory Controller
SHDN FWUP
SUPC
VDDBU
POR
NRSTB
ERASE
RSTC PIOB
NRST
8-channel 12-bit ADC 10-bit ADC TWI0 TWI1
UART
USART0 USART1 USART2 USART3
TC0 TC1 TC2
SPI
SSC
HSMCI
NCS2
NANDOE, NANDWE
PIOA
PIOC
1 0 I 77 EF A 3 G D K1 S3 S3 K3 X3 D3 D RI0 R0 R0 222 S3 K S O H L3 XD D S VR AN TR -AD 2B TW C C PC O IS R TX -CT-RT-SC-RD-TX DC LK A B D DT WM WM UU C IO IO -NP S M M 00000 2B DD 12B D0 D1 0- -TW 1 -T 0-T 0-T -P 0-P A -A WD K0 0 VD TS TS CK DX XD D 0A B 0 S CRSR T HL -A -A B0 T C LK IO IO M WM PC G 12 EF N TW TC T T R TR PW P AD D DV A A
A7 A K TK TF TD RD RF RK -D CD C 0 DA
SAM3U Series
3
Figure 2-2.
SE
L
TD TDI O TM /TR SA TC /SW CE S K /S DIO WO W CL K
JT AG
TST
System Controller
JTAG & Serial Wire
HS UTMI Transceiver
VD
VD
MASTER
SLAVE
DI
DO
II TM P M DP DM U D G FSDFSDHS HS VD VB D D D D
N UT
4
In-Circuit Emulator
SAM3U Series
Voltage Regulator
PCK0-PCK2
EBI
PLLA PMC
SysTick Counter
UPLL Cortex-M3 Processor Fmax 96MHz MPU I/D S DMA
OSC 3-20 M
RC Osc. 12/8/4 M
XIN XOUT
N V I C
USB Device HS
NAND Flash Controller & ECC NANDRDY
100-pin SAM3U4/2/1C Block Diagram
WDT
5-layer AHB Bus Matrix
D0-D7 A0 A1 A2-A7 Nand Flash SRAM (4KBytes)
VDDUTMI
SM BOD RC 32k
OSC 32K 8 GPBREG
Flash Unique Identifier
VDDCORE
FLASH 2x128KBytes 1x128 KBytes 1x 64kbytes ROM 16KBytes Peripheral Bridge APB
SRAM0 32KBytes 16KBytes 8KBytes
SRAM1 16KBytes 16KBytes 8KBytes
Peripheral DMA Controller
4-Channel DMA
NCS0 NCS1 NRD NWE
XIN32 XOUT32
RTT RTC PDC PDC PDC PWM PDC PDC
Static Memory Controller
NANDALE NANDCLE
FWUP
SUPC
POR
VDDBU
NRSTB
ERASE
TWI
UART
RSTC
4-channel 12-bit ADC 10-bit ADC
USART0 USART1 USART2
TC0 TC1 TC2
SPI
SSC
HSMCI
NANDOE, NANDWE
NRST
PIOA PIOB
EF A
AD
B 12
VR
VR AD
I 2 2 2 2 2 0 I0 0 0 33 G D3 3 D CK A 222 S3 K S O TS S K X D CD R SR TR MH ML N XD D C PC O IS TR A 2B TW W R TX -C -RT -SC-RD-TX D LK A B DD W W T DA 2B D0- D1 UU C IO IO -NP S M M S0 S0 K0 X0 D0 -T 0-T 0-T -P 0-P 0 VD D1 A 0-A T 0A B 0 S C RT SC RD TX HL -A B LK IO IO M WM G PC 12 N TC T T TR PW P AD D
EF
3AK TK TF TD RD RF RK -DA CD C 0 DA
6430BS-ATARM-01-Sep-09
SAM3U Series
3. Signal Description
Table 3-1 gives details on the signal names classified by peripheral. Table 3-1.
Signal Name
Signal Description List
Function Type Power Supplies Active Level Voltage Reference Comments
VDDIO VDDIN VDDOUT VDDUTMII GNDUTMII VDDBU GNDBU VDDPLL GNDPLL VDDANA GNDANA VDDCORE GND
Peripherals I/O Lines Power Supply Voltage Regulator Input Voltage Regulator Output USB UTMI+ Interface Power Supply USB UTMI+ Interface Ground Backup I/O Lines Power Supply Backup Ground PLL A, UPLL and OSC 3-20 MHz Power Supply PLL A, UPLL and OSC 3-20 MHz Ground ADC Analog Power Supply ADC Analog Ground Core, Memories and Peripherals Chip Power Supply Ground
Power Power Power Power Ground Power Ground Power Ground Power Ground Power Ground
1.62V to 3.6V 1.8V to 3.6V 1.8V 3.0V to 3.6V
1.62V to 3.6V
1.62 V to 1.95V
2.0V to 3.6V
1.62V to 1.95V
Clocks, Oscillators and PLLs XIN XOUT XIN32 XOUT32 VBG PCK0 - PCK2 Main Oscillator Input Main Oscillator Output Slow Clock Oscillator Input Slow Clock Oscillator Output Bias Voltage Reference Programmable Clock Output Input Output Input Output Analog Output Shutdown, Wakeup Logic push/pull 0: The device is in backup mode 1: The device is running (not in backup mode) Needs external pull-up VDDIO VDDBU VDDPLL
SHDN
Shut-Down Control
Output
VDDBU
FWUP
Force Wake-Up Input
Input
Low
Serial Wire/JTAG Debug Port (SWJ-DP) TCK/SWCLK TDI TDO/TRACESWO TMS/SWDIO JTAGSEL Test Clock/Serial Wire Clock Test Data In Test Data Out/Trace Asynchronous Data Out Test Mode Select/Serial Wire Input/Output JTAG Selection Input Input Output Input Input High VDDBU VDDIO No pull-up resistor No pull-up resistor
No pull-up resistor Internal permanent pull-down
5
6430BS-ATARM-01-Sep-09
Table 3-1.
Signal Name
Signal Description List (Continued)
Function Type Flash Memory Active Level Voltage Reference Comments
ERASE
Flash and NVM Configuration Bits Erase Command
Input
High
VDDBU
Internal permanent 15K pulldown
Reset/Test NRST NRSTB TST Microcontroller Reset Asynchronous Microcontroller Reset Test Select I/O Input Input Universal Asynchronous Receiver Transceiver - UART URXD UTXD UART Receive Data UART Transmit Data Input Output PIO Controller - PIOA - PIOB - PIOC *Schmitt Trigger (1) Reset State: *PIO Input *Internal pullup enabled *Schmitt Trigger (2) Reset State: *PIO Input *Internal pullup enabled *Schmitt Trigger(3) Reset State: *PIO Input *Internal pullup enabled Low Low VDDBU VDDIO Internal permanent pullup Internal permanent pullup Internal permanent pulldown
PA0 - PA31
Parallel IO Controller A
I/O
PB0 - PB31
Parallel IO Controller B
I/O
VDDIO
PC0 - PC31
Parallel IO Controller C
I/O
External Bus Interface D0 - D15 A0 - A23 NWAIT Data Bus Address Bus External Wait Signal I/O Output Input Static Memory Controller - SMC NCS0 - NCS3 NWR0 - NWR1 NRD NWE NBS0 - NBS1 Chip Select Lines Write Signal Read Signal Write Enable Byte Mask Signal Output Output Output Output Output NAND Flash Controller - NFC NANDOE NANDWE NANDRDY NAND Flash Output Enable NAND Flash Write Enable NAND Ready Output Output Input Low Low Low Low Low Low Low Low
6
SAM3U Series
6430BS-ATARM-01-Sep-09
SAM3U Series
Table 3-1.
Signal Name
Signal Description List (Continued)
Function Type Active Level Voltage Reference Comments
High Speed Multimedia Card Interface - HSMCI CK CDA DA0 - DA7 Multimedia Card Clock Multimedia Card Slot A Command Multimedia Card Slot A Data I/O I/O I/O
Universal Synchronous Asynchronous Receiver Transmitter - USARTx SCKx TXDx RXDx RTSx CTSx DTR0 DSR0 DCD0 RI0 USARTx Serial Clock USARTx Transmit Data USARTx Receive Data USARTx Request To Send USARTx Clear To Send USART0 Data Terminal Ready USART0 Data Set Ready USART0 Data Carrier Detect USART0 Ring Indicator I/O I/O Input Output Input I/O Input Output Input Synchronous Serial Controller - SSC TD RD TK RK TF RF SSC Transmit Data SSC Receive Data SSC Transmit Clock SSC Receive Clock SSC Transmit Frame Sync SSC Receive Frame Sync Output Input I/O I/O I/O I/O Timer/Counter - TC TCLKx TIOAx TIOBx TC Channel x External Clock Input TC Channel x I/O Line A TC Channel x I/O Line B Input I/O I/O
Pulse Width Modulation Controller- PWMC PWMHx PWM Waveform Output High for channel x PWM Waveform Output Low for channel x PWMLx Output Output only output in complementary mode when dead time insertion is enabled
PWMFI0-2
PWM Fault Input
Input Serial Peripheral Interface - SPI
MISO MOSI SPCK NPCS0 NPCS1 - NPCS3
Master In Slave Out Master Out Slave In SPI Serial Clock SPI Peripheral Chip Select 0 SPI Peripheral Chip Select
I/O I/O I/O I/O Output Low Low
7
6430BS-ATARM-01-Sep-09
Table 3-1.
Signal Name
Signal Description List (Continued)
Function Type Two-Wire Interface - TWI Active Level Voltage Reference Comments
TWDx TWCKx
TWIx Two-wire Serial Data TWIx Two-wire Serial Clock
I/O I/O
12-bit Analog-to-Digital Converter - ADC12B AD12Bx AD12BTRG AD12BVREF Analog Inputs ADC Trigger ADC Reference Analog Input Analog 10-bit Analog-to-Digital Converter - ADC ADx ADTRG ADVREF Analog Inputs ADC Trigger ADC Reference Analog Input Analog Fast Flash Programming Interface - FFPI PGMEN0-PGMEN2 Programming Enabling PGMM0-PGMM3 PGMD0-PGMD15 PGMRDY PGMNVALID PGMNOE PGMCK PGMNCMD Programming Mode Programming Data Programming Ready Data Direction Programming Read Programming Clock Programming Command Input Input I/O Output Output Input Input Input USB High Speed Device - UDPHS DFSDM DFSDP DHSDM DHSDP Notes: USB Device Full Speed Data USB Device Full Speed Data + USB Device High Speed Data USB Device High Speed Data + Analog Analog Analog Analog VDDUTMII Low High Low Low VDDIO
1. PIOA: Schmitt Trigger on all except PA14 on 100 and 144 packages. 2. PIOB: Schmitt Trigger on all except PB9 to PB16, PB25 to PB31 on 100 and 144 packages. 3. PIOC: Schmitt Trigger on all except PC20 to PC27 on 144 package.
3.1
Design Considerations
In order to facilitate schematic capture when using a SAM3U design, Atmel provides a "Schematics Checklist" Application note. Please visit http://www.atmel.com/products/AT91/
8
SAM3U Series
6430BS-ATARM-01-Sep-09
SAM3U Series
4. Package and Pinout
The SAM3U4/2/1E is available in 144-lead LQFP and 144-ball LFBGA packages. The SAM3U4/2/1C is available in 100-lead LQFP and 100-ball LFBGA packages.
4.1
4.1.1
SAM3U4/2/1E Package and Pinout
144-ball LFBGA Package Outline The 144-Ball LFBGA package has a 0.8 mm ball pitch and respects Green Standards. Its dimensions are 10 x 10 x 1.4 mm. Figure 4-1. Orientation of the 144-ball LFBGA Package
TOP VIEW
12 11 10 9 8 7 6 5 4 3 2 1 ABCDEF GHJ
BALL A1
KLM
4.1.2
144-lead LQFP Package Outline Figure 4-2. Orientation of the 144-lead LQFP Package
108 109
73 72
144 1 36
37
9
6430BS-ATARM-01-Sep-09
4.1.3 Table 4-1.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
144-lead LQFP Pinout 144-pin SAM3U4/2/1E Pinout
TDI VDDOUT VDDIN TDO/TRACESWO PB31 PB30 TMS/SWDIO PB29 TCK/SWCLK PB28 NRST PB27 PB26 PB25 PB24 VDDCORE VDDIO GND PB23 PB22 PB21 PC21 PB20 PB19 PB18 PB17 VDDCORE PC14 PB14 PB10 PB9 PC19 GNDPLL VDDPLL XOUT XIN 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 DHSDP DHSDM VBG VDDUTMI DFSDM DFSDP GNDUTMI VDDCORE PA28 PA29 PC22 PA31 PC23 VDDCORE VDDIO GND PB0 PC24 PB1 PC25 PB2 PC26 PB11 GND PB12 PB13 PC27 PA27 PB5 PB6 PB7 PB8 PC28 PC29 PC30 PC31 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 VDDANA ADVREF GNDANA AD12BVREF PA22/PGMD14 PA30 PB3 PB4 PC15 PC16 PC17 PC18 VDDIO VDDCORE PA13/PGMD5 PA14/PGMD6 PC10 GND PA15/PGMD7 PC11 PA16/PGMD8 PC12 PA17/PGMD9 PB16 PB15 PC13 PA18/PGMD10 PA19/PGMD11 PA20/PGMD12 PA21/PGMD13 PA23/PGMD15 VDDIO PA24 PA25 PA26 PC20 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 PA0/PGMNCMD PC0 PA1/PGMRDY PC1 PA2/PGMNOE PC2 PA3/PGMNVALID PC3 PA4/PGMM0 PC4 PA5/PGMM1 PC5 PA6/PGMM2 PC6 PA7/PGMM3 PC7 VDDCORE GND VDDIO PA8/PGMD0 PC8 PA9/PGMD1 PC9 PA10/PGMD2 PA11/PGMD3 PA12/PGMD4 FWUP SHDN ERASE TST VDDBU GNDBU NRSTB JTAGSEL XOUT32 XIN32
10
SAM3U Series
6430BS-ATARM-01-Sep-09
SAM3U Series
4.1.4 Table 4-2.
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12
144-ball LFBGA Pinout 144-ball SAM3U4/2/1E Pinout
VBG VDDUTMI PB9 PB10 PB19 PC21 PB26 TCK/SWCLK PB30 TDO/TRACESWO XIN32 XOUT32 VDDCORE GNDUTMI XOUT PB14 PB17 PB22 PB25 PB29 VDDIN JTAGSEL ERASE SHDN DFSDP DHSDP XIN VDDPLL PB18 PB20 PB27 TMS/SWDIO VDDOUT NRSTB TST FWUP D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 DFSDM DHSDM GNDPLL PC14 PB21 PB23 PB24 PB28 TDI VDDBU PA10/PGMD2 PA11/PGMD3 PC22 PA28 PC19 VDDCORE GND VDDIO GNDBU NRST PB31 PA12/PGMD4 PA8/PGMD0 PC8 PA31 PA29 PC23 VDDCORE VDDIO GND GND VDDIO PC9 PA9/PGMD1 VDDCORE PC7 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 PB0 PC26 PB2 PC25 PB1 GND GND VDDCORE PC4 PA6/PGMM2 PA7/PGMM3 PC6 PC24 PC27 PA27 PB12 PB11 GND VDDCORE PB16 PB15 PC3 PA5/PGMM1 PC5 PB5 PB6 PC28 PB8 PB13 VDDIO PA13/PGMD5 PA17/PGMD9 PC13 PA2/PGMNOE PA3/PGMNVALID PA4/PGMM0 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 PB7 PC31 PC29 PB3 PB4 PA14/PGMD6 PA16/PGMD8 PA18/PGMD10 PC20 PA1/PGMRDY PC1 PC2 PC30 ADVREF AD12BVREF PA22/PGMD14 PC17 PC10 PC12 PA19/PGMD11 PA23/PGMD15 PA0/PGMNCMD PA26 PC0 VDDANA GNDANA PA30 PC15 PC16 PC18 PA15/PGMD7 PC11 PA20/PGMD12 PA21/PGMD13 PA24 PA25
11
6430BS-ATARM-01-Sep-09
4.2
4.2.1
SAM3U4/2/1C Package and Pinout
100-lead LQFP Package Outline Figure 4-3. Orientation of the 100-lead LQFP Package
75 76
51 50
100 1 25
26
4.2.2
100-ball LFBGA Package Outline Figure 4-4. Orientation of the 100-ball LFBGA Package
TOP VIEW 1 2 3 4 5 6 7 8 9 10
A B C D E F G H J K
12
SAM3U Series
6430BS-ATARM-01-Sep-09
SAM3U Series
4.2.3 Table 4-3.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
100-lead LQFP Pinout 100-pin SAM3U4/2/1C1 Pinout
VDDANA ADVREF GNDANA AD12BVREF PA22/PGMD14 PA30 PB3 PB4 VDDCORE PA13/PGMD5 PA14/PGMD6 PA15/PGMD7 PA16/PGMD8 PA17/PGMD9 PB16 PB15 PA18/PGMD10 PA19/PGMD11 PA20/PGMD12 PA21/PGMD13 PA23/PGMD15 VDDIO PA24 PA25 PA26 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 PA0/PGMNCMD PA1/PGMRDY PA2/PGMNOE PA3/PGMNVALID PA4/PGMM0 PA5/PGMM1 PA6/PGMM2 PA7/PGMM3 VDDCORE GND VDDIO PA8/PGMD0 PA9/PGMD1 PA10/PGMD2 PA11/PGMD3 PA12/PGMD4 FWUP ERASE TST VDDBU GNDBU NRSTB JTAGSEL XOUT32 XIN32 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 TDI VDDOUT VDDIN TDO/TRACESWO TMS/SWDIO TCK/SWCLK NRST PB24 VDDCORE VDDIO GND PB23 PB22 PB21 PB20 PB19 PB18 PB17 PB14 PB10 PB9 GNDPLL VDDPLL XOUT XIN 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 DHSDP DHSDM VBG VDDUTMI DFSDM DFSDP GNDUTMI VDDCORE PA28 PA29 PA31 VDDCORE VDDIO GND PB0 PB1 PB2 PB11 PB12 PB13 PA27 PB5 PB6 PB7 PB8
13
6430BS-ATARM-01-Sep-09
4.2.4
100-ball LFBGA Pinout
Table 4-4.
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 C1 C2 C3 C4 C5
100-ball SAM3U4/2/1C Pinout
VBG XIN XOUT PB17 PB21 PB23 TCK/SWCLK VDDIN VDDOUT XIN32 VDDCORE GNDUTMI VDDUTMI PB10 PB18 PB24 NRST C6 C7 C8 C9 C10 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 PB22 TMS/SWDIO NRSTB JTAGSEL VDDBU DFSDM DHSDM VDDPLL VDDCORE PB20 ERASE TST FWUP PA11/PGMD3 PA12/PGMD4 PA29 GND PA28 PB9 GNDBU VDDIO VDDCORE PA10/PGMD2 PA9/PGMD1 PA8/PGMD0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 H1 H2 H3 H4 H5 PB1 PB12 VDDIO PA31 VDDIO GND PB16 PA6/PGMM2 VDDCORE PA7/PGMM3 PB11 PB2 PB0 PB13 VDDCORE GND PB15 PA3/PGMNVALID PA5/PGMM1 PA4/PGMM0 VDDCORE PB5 PA27 PA22/PGMD14 PA13/PGMD5 H6 H7 H8 H9 H10 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 PA15/PGMD7 PA18/PGMD10 PA24 PA1/PGMRDY PA2/PGMNOE PB6 PB8 ADVREF PA30 PB3 PA16/PGMD8 PA19/PGMD11 PA21/PGMD13 PA26 PA0/PGMNCMD PB7 VDDANA GNDANA AD12BVREF PB4 PA14/PGMD6 PA17/PGMD9 PA20/PGMD12 PA23/PGMD15 PA25
TDO/TRACESWO TDI XOUT32 DFSDP DHSDP GNDPLL PB14 PB19
14
SAM3U Series
6430BS-ATARM-01-Sep-09
SAM3U Series
5. Power Considerations
5.1 Power Supplies
The SAM3U product has several types of power supply pins: * VDDCORE pins: Power the core, the embedded memories and the peripherals; voltage ranges from 1.62V and 1.95V. * VDDIO pins: Power the Peripherals I/O lines; voltage ranges from 1.62V and 3.6V. * VDDIN pin: Powers the Voltage regulator * VDDOUT pin: It is the output of the voltage regulator. * VDDBU pin: Powers the Slow Clock oscillator and a part of the System Controller; voltage ranges from 1.62V and 3.6V. VDDBU must be supplied before or at the same time than VDDIO and VDDCORE. * VDDPLL pin: Powers the PLL A, UPLL and 3-20 MHz Oscillator; voltage ranges from 1.62V and 1.95V. * VDDUTMI pin: Powers the UTMI+ interface; voltage ranges from 3.0V and 3.6V, 3.3V nominal. * VDDANA pin: Powers the ADC cells; voltage ranges from 2.0V and 3.6V. Ground pins GND are common to VDDCORE and VDDIO pins power supplies. Separated ground pins are provided for VDDBU, VDDPLL, VDDUTMI and VDDANA. These ground pins are respectively GNDBU, GNDPLL, GNDUTMI and GNDANA.
5.2
Voltage Regulator
The SAM3U embeds a voltage regulator that is managed by the Supply Controller. This internal regulator is intended to supply the internal core of SAM3U but can be used to supply other parts in the application. It features two different operating modes: * In Normal mode, the voltage regulator consumes less than 700 A static current and draws 150 mA of output current. Internal adaptive biasing adjusts the regulator quiescent current depending on the required load current. In Wait Mode or when the output current is low, quiescent current is only 7A. * In Shutdown mode, the voltage regulator consumes less than 1 A while its output is driven internally to GND. The default output voltage is 1.80V and the start-up time to reach Normal mode is inferior to 400 s. For adequate input and output power supply decoupling/bypassing, refer to the Voltage Regulator section in the Electrical Characteristics section of the datasheet.
5.3
Typical Powering Schematics
The SAM3U supports a 1.62V-3.6V single supply mode. The internal regulator input connected to the source and its output feeds VDDCORE. Figure 5-6 shows the power schematics.
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Figure 5-1.
Single Supply
VDDBU
VDDUTMI
VDDANA
VDDIO
Main Supply (1.62V-3.6V)
VDDIN Voltage Regulator VDDOUT
VDDCORE
VDDPLL
Note:
Restrictions With Main Supply < 2.4 V, USB and ADC are not usable. With Main Supply 2.4V and < 3V, USB is not usable. With Main Supply 3V, all peripherals are usable.
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Figure 5-2. Core Externally Supplied
VDDBU
VDDUTMI
VDDANA
Main Supply (1.62V-3.6V)
VDDIO
VDDIN Voltage Regulator VDDOUT
VDDCORE Supply (1.62V-1.95V) VDDCORE
VDDPLL
Note:
Restrictions With Main Supply < 2.4 V, USB and ADC are not usable. With Main Supply 2.4V and < 3V, USB is not usable. With Main Supply 3V, all peripherals are usable.
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Figure 5-3.
Backup Batteries Used
FWUP
SHDN
Backup Batteries VDDBU
VDDUTMI
VDDANA
VDDIO
VDDIN Main Supply (1.62V-3.6V) VDDOUT Voltage Regulator
VDDCORE
VDDPLL
Note:
Restrictions With Main Supply < 2.4 V, USB and ADC are not usable. With Main Supply 2.4V and < 3V, USB is not usable. With Main Supply 3V, all peripherals are usable.
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5.4 Active Mode
Active mode is the normal running mode with the core clock running from the fast RC oscillator, the main crystal oscillator or the PLLA. The power management controller can be used to adapt the frequency and to disable the peripheral clocks.
5.5
Low Power Modes
The various low power modes of the SAM3U are described below:
5.5.1
Backup Mode The purpose of backup mode is to achieve the lowest power consumption possible in a system which is performing periodic wake-ups to perform tasks but not requiring fast startup time (<0.5ms). The Supply Controller, zero-power power-on reset, RTT, RTC, Backup registers and 32 kHz Oscillator (RC or crystal oscillator selected by software in the Supply Controller) are running. The regulator and the core supply are off. Backup Mode is based on the Cortex-M3 deep-sleep mode with the voltage regulator disabled. The SAM3U Series can be awakened from this mode through the Force Wake-Up pin (FWUP), and Wake-Up input pins WUP0 to WUP15, Supply Monitor, RTT or RTC wake-up event. Current Consumption is 2.5 A typical on VDDBU. Backup mode is entered by using WFE instructions with the SLEEPDEEP bit in the System Control Register of the Cortex-M3 set to 1. (See the Power management description in The ARM Cortex M3 Processor section of the product datasheet). Exit from Backup mode happens if one of the following enable wake up events occurs: * FWUP pin (low level, configurable debouncing) * WKUPEN0-15 pins (level transition, configurable debouncing) * SM alarm * RTC alarm * RTT alarm
5.5.2
Wait Mode The purpose of the wait mode is to achieve very low power consumption while maintaining the whole device in a powered state for a startup time of less than 10 s. In this mode, the clocks of the core, peripherals and memories are stopped. However, the core, peripherals and memories power supplies are still powered. From this mode, a fast start up is available. This mode is entered via Wait for Event (WFE) instructions with LPM = 1 (Low Power Mode bit in PMC_FSMR). The Cortex-M3 is able to handle external events or internal events in order to wake-up the core (WFE). By configuring the external lines WUP0-15 as fast startup wake-up pins (refer to Section 5.7 "Fast Start-Up"). RTC or RTT Alarm and USB wake-up events can be used to wake up the CPU (exit from WFE). Current Consumption in Wait mode is typically 15 A on VDDIN if the internal voltage regulator is used or 8 A on VDDCORE if an external regulator is used.
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Entering Wait Mode: * Select the 4/8/12 MHz Fast RC Oscillator as Main Clock * Set the LPM bit in the PMC Fast Startup Mode Register (PMC_FSMR) * Execute the Wait-For-Event (WFE) instruction of the processor
Note:
Internal Main clock resynchronization cycles are necessary between the writing of MOSCRCEN bit and the effective entry in Wait mode. Depending on the user application, Waiting for MOSCRCEN bit to be cleared is recommended to ensure that the core will not execute undesired instructions.
5.5.3
Sleep Mode The purpose of sleep mode is to optimize power consumption of the device versus response time. In this mode, only the core clock is stopped. The peripheral clocks can be enabled. This mode is entered via Wait for Interrupt (WFI) or Wait for Event (WFE) instructions with LPM = 0 in PMC_FSMR. The processor can be woke up from an interrupt if WFI instruction of the Cortex M3 is used, or from an event if the WFE instruction is used to enter this mode.
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5.5.4 Low Power Mode Summary Table The modes detailed above are the main low power modes. Each part can be set to on or off separately and wake up sources can be individually configured. Table 5-1 below shows a summary of the configurations of the low power modes. Low Power Mode Configuration Summary
Table 5-1.
Mode
SUPC, 32 kHz Oscillator RTC RTT Backup Registers, Core POR Memory (VDDBU Region) Regulator Peripherals
Mode Entry WFE
PIO State Potential Wake Up Core at while in Low PIO State Consumption Wake-up (2) (3) Sources Wake Up Power Mode at Wake Up Time(1) PIOA & PIOB & PIOC Inputs with pull ups
Backup Mode
ON
FWUP pin WUP0-15 pins OFF OFF +SLEEPDEEP BOD alarm SHDN =0 (Not powered) RTC alarm bit = 1 RTT alarm WFE
Reset
Previous state saved
2.5 A typ(4)
< 0.5 ms
Wait Mode
ON
Any Event from: Fast startup through ON Powered Clocked +SLEEPDEEP WUP0-15 pins back RTC alarm bit = 0 SHDN =1 (Not clocked) +LPM bit = 1 RTT alarm USB wake-up Entry mode =WFI Interrupt Only; Entry mode =WFE Any WFE or WFI Enabled Interrupt ON Powered(7) +SLEEPDEEP and/or Any Event Clocked from: Fast start-up back bit = 0 SHDN =1 (Not clocked) through WUP0-15 +LPM bit = 0 pins RTC alarm RTT alarm USB wake-up
Previous state saved
Unchanged 8 A/15 A (5) < 10 s
Sleep Mode
ON
Previous state saved
Unchanged
(6)
(6)
Notes:
1. When considering wake-up time, the time required to start the PLL is not taken into account. Once started, the device works with the 4/8/12 MHz Fast RC oscillator. The user has to add the PLL start-up time if it is needed in the system. The wake-up time is defined as the time taken for wake up until the first instruction is fetched. 2. The external loads on PIOs are not taken into account in the calculation. 3. BOD current consumption is not included. 4. Current consumption on VDDBU. 5. 8 A or VDDCORE, 15 A on VDDIN. 6. Depends on MCK frequency. 7. In this mode the core is supplied and not clocked but some peripherals can be clocked.
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5.6
Wake-up Sources
The wake-up events allow the device to exit backup mode. When a wake-up event is detected, the Supply Controller performs a sequence which automatically reenables the core power supply.
Figure 5-4.
Wake-up Source
SMEN sm_int RTCEN rtc_alarm RTTEN rtt_alarm FWUPDBC SLCK FWUPEN Falling Edge Detector Debouncer FWUP Core Supply Restart
FWUP
WKUPT0 Falling/Rising Edge Detector WKUPT1 Falling/Rising Edge Detector WKUPT15 Falling/Rising Edge Detector
WKUPEN0
WKUPIS0
WKUP0
WKUPDBC WKUPEN1 WKUPIS1 SLCK Debouncer WKUPS
WKUP1
WKUPEN15
WKUPIS15
WKUP15
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5.7 Fast Start-Up
The SAM3U allows the processor to restart in a few microseconds while the processor is in wait mode. A fast start up can occur upon detection of a low level on one of the 19 wake-up inputs. The fast restart circuitry, as shown in Figure 5-5, is fully asynchronous and provides a fast startup signal to the Power Management Controller. As soon as the fast start-up signal is asserted, the PMC automatically restarts the embedded 4/8/12 MHz fast RC oscillator, switches the master clock on this 4/8/12 MHz clock and reenables the processor clock. Figure 5-5. Fast Start-Up Sources
USBEN usb_wakeup RTCEN rtc_alarm
RTTEN rtt_alarm
FSTT0
Falling/Rising Edge Detector
WKUP0
fast_restart FSTT1
WKUP1
Falling/Rising Edge Detector
FSTT15
Falling/Rising Edge Detector
WKUP15
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6. Input/Output Lines
The SAM3U has different kinds of input/output (I/O) lines, such as general purpose I/Os (GPIO) and system I/Os. GPIOs can have alternate functions thanks to multiplexing capabilities of the PIO controllers. The same GPIO line can be used whether it is in IO mode or used by the multiplexed peripheral. System I/Os are pins such as test pin, oscillators, erase pin, analog inputs or debug pins. With a few exceptions, the I/Os have input schmitt triggers. Refer to the footnotes associated with "PIO Controller - PIOA - PIOB - PIOC" on page 6 within Table 3-1, "Signal Description List,".
6.1
General Purpose I/O Lines (GPIO)
GPIO Lines are managed by PIO Controllers. All I/Os have several input or output modes such as, pull-up, input schmitt triggers, multi-drive (open-drain), glitch filters, debouncing or input change interrupt. Programming of these modes is performed independently for each I/O line through the PIO controller user interface. For more details, refer to the product PIO controller section. The input output buffers of the PIO lines are supplied through VDDIO power supply rail. The SAM3U embeds high speed pads able to handle up to 65 MHz for HSMCI and SPI clock lines and 35 MHz on other lines. See product AC Characteristics for more details. Typical pull-up value is 100 k for all I/Os. Each I/O line also embeds an ODT (On-Die Termination), (see Figure 6-1 below). ODT consists of an internal series resistor termination scheme for impedance matching between the driver output (SAM3) and the PCB track impedance preventing signal reflection. The series resistor helps to reduce IOs switching current (di/dt) thereby reducing in turn, EMI. It also decreases overshoot and undershoot (ringing) due to inductance of interconnect between devices or between boards. In conclusion, ODT helps reducing signal integrity issues. Figure 6-1. On-Die Termination schematic
Z0 ~ Zout + Rodt
ODT 36 Ohms Typ.
Rodt
Receiver SAM3 Driver with Zout ~ 10 Ohms PCB Trace Z0 ~ 50 Ohms
6.2
System I/O Lines
System I/O lines are pins used by oscillators, test mode, reset, flash erase and JTAG to name but a few.
6.3
Serial Wire JTAG Debug Port (SWJ-DP)
The SWJ-DP pins are TCK/SWCLK, TMS/SWDIO, TDO/SWO, TDI and commonly provided on a standard 20-pin JTAG connector defined by ARM. For more details about voltage reference and reset state, refer to Table 3-1, "Signal Description List,"
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The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. It integrates a permanent pull-down resistor of about 15 k to GNDBU, so that it can be left unconnected for normal operations. By default, the JTAG Debug Port is active. If the debugger host wants to switch to the Serial Wire Debug Port, it must provide a dedicated JTAG sequence on TMS/SWDIO and TCK/SWCLK which disables the JTAG-DP and enables the SW-DP. When the Serial Wire Debug Port is active, TDO/TRACESWO can be used for trace. The asynchronous TRACE output (TRACESWO) is multiplexed with TDO. So the asynchronous trace can only be used with SW-DP, not JTAG-DP. All the JTAG signals are supplied with VDDIO except JTAGSEL, supplied by VDDBU.
6.4
Test Pin
The TST pin is used for JTAG Boundary Scan Manufacturing Test or fast flash programming mode of the SAM3U series. The TST pin integrates a permanent pull-down resistor of about 15 k to GND, so that it can be left unconnected for normal operations.To enter fast programming mode, see the Fast Flash Programming Interface (FFPI) section. For more on the manufacturing and test mode, refer to the "Debug and Test" section of the product datasheet.
6.5
NRST Pin
The NRST pin is bidirectional. It is handled by the on-chip reset controller and can be driven low to provide a reset signal to the external components or asserted low externally to reset the microcontroller. It will reset the Core and the peripherals except the Backup region (RTC, RTT and Supply Controller). There is no constraint on the length of the reset pulse and the reset controller can guarantee a minimum pulse length. The NRST pin integrates a permanent pull-up resistor to VDDIO of about 100 k.
6.6
NRSTB Pin
The NRSTB pin is input only and enables asynchronous reset of the SAM3U when asserted low. The NRSTB pin integrates a permanent pull-up resistor of about 15 k. This allows connection of a simple push button on the NRSTB pin as a system-user reset. In all modes, this pin will reset the chip including the Backup region (RTC, RTT and Supply Controller). It reacts as the Power-on reset. It can be used as an external system reset source. In harsh environments, it is recommended to add an external capacitor (10 nF) between NRSTB and VDDBU. (For filtering values refer to the I/O characteristics section of the product Electrical Characteristics.) It embeds an anti-glitch filter.
6.7
ERASE Pin
The ERASE pin is used to reinitialize the Flash content and some of its NVM bits. It integrates a permanent pull-down resistor of about 15 k to GND, so that it can be left unconnected for normal operations. This pin is debounced by SCLK to improve the glitch tolerance. When the ERASE pin is tied high during less than 100 ms, it is not taken into account. The pin must be tied high during more than 220 ms to perform the reinitialization of the Flash. Even in all low power modes, asserting the pin will automatically start-up the chip and erase the Flash.
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7. Processor and Architecture
7.1 ARM Cortex-M3 Processor
* Version 2.0 * Thumb-2 (ISA) subset consisting of all base Thumb-2 instructions, 16-bit and 32-bit. * Harvard processor architecture enabling simultaneous instruction fetch with data load/store. * Three-stage pipeline. * Single cycle 32-bit multiply. * Hardware divide. * Thumb and Debug states. * Handler and Thread modes. * Low latency ISR entry and exit.
7.2
APB/AHB Bridges
The SAM3U product embeds two separated APB/AHB bridges: * low speed bridge * high speed bridge This architecture enables to make concurrent accesses on both bridges. All the peripherals are on the low-speed bridge except SPI, SSC and HSMCI. The UART, 10-bit ADC (ADC), 12-bit ADC (ADC12B), TWI0-1, USART0-3, PWM have dedicated channels for the Peripheral DMA Channels (PDC). These peripherals can not use the DMA Controller. The high speed bridge regroups the SSC, SPI and HSMCI. These three peripherals do not have PDC channels but can use the DMA with the internal FIFO for Channel buffering. Note that the peripherals of the two bridges are clocked by the same source: MCK.
7.3
Matrix Masters
The Bus Matrix of the SAM3U device manages 5 masters, which means that each master can perform an access concurrently with others to an available slave. Each master has its own decoder and specifically defined bus. In order to simplify the addressing, all the masters have the same decoding. Table 7-1.
Master 0 Master 1 Master 2 Master 3 Master 4
List of Bus Matrix Masters
Cortex-M3 Instruction/Data Cortex-M3 System Peripheral DMA Controller (PDC) USB Device High Speed DMA DMA Controller
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7.4 Matrix Slaves
The Bus Matrix of the SAM3U manages 10 slaves. Each slave has its own arbiter, allowing a different arbitration per slave. Table 7-2.
Slave 0 Slave 1 Slave 2 Slave 3 Slave 4 Slave 5 Slave 6 Slave 7 Slave 8 Slave 9
List of Bus Matrix Slaves
Internal SRAM0 Internal SRAM1 Internal ROM Internal Flash 0 Internal Flash 1 USB Device High Speed Dual Port RAM (DPR) NAND Flash Controller RAM External Bus Interface Low Speed Peripheral Bridge High Speed Peripheral Bridge
7.5
Master to Slave Access
All the Masters can normally access all the Slaves. However, some paths do not make sense, for example allowing access from the USB Device High speed DMA to the Internal Peripherals. Thus, these paths are forbidden or simply not wired, and shown as "-" in Table 7-3 below.
Table 7-3.
SAM3U Master to Slave Access
0 Cortex-M3 I/D Bus - - X X X - - - - - 1 Cortex-M3 S Bus X X - - - X X X X X 2 3 USB Device High Speed DMA X X X - - - X X - - 4 DMA Controller X X X - - - X X - -
Slaves 0 1 2 3 4 5 6 7 8 9 Internal SRAM0 Internal SRAM1 Internal ROM Internal Flash 0 Internal Flash 1
Masters
PDC X X X - - - X X X X
USB Device High Speed Dual Port RAM (DPR) NAND Flash Controller RAM External Bus Interface Low Speed Peripheral Bridge High Speed Peripheral Bridge
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7.6
DMA Controller
* Acting as one Matrix Master * Embeds 4 channels: - 3 channels with 8 bytes/FIFO for Channel Buffering - 1 channel with 32 bytes/FIFO for Channel Buffering * Linked List support with Status Write Back operation at End of Transfer * Word, HalfWord, Byte transfer support. * Handles high speed transfer of SPI, SSC and HSMCI (peripheral to memory, memory to peripheral) * Memory to memory transfer * Can be triggered by PWM and T/C which enables to generate waveforms though the External Bus Interface The DMA controller can handle the transfer between peripherals and memory and so receives the triggers from the peripherals listed below. The hardware interface numbers are also given in Table 7-4 below. Table 7-4. DMA Controller
Channel T/R Transmit/Receive Transmit Receive Transmit Receive Trigger Trigger Trigger DMA Channel HW interface Number 0 1 2 3 4 5 6 7
Instance name HSMCI SPI SPI SSC SSC PWM Event Line 0 PWM Event Line 1 TIO Output of TImer Counter Channel 0
7.7
Peripheral DMA Controller
* * Handles data transfer between peripherals and memories Nineteen channels - - - - - * Two for each USART Two for the UART Two for each Two Wire Interface One for the PWM One for each Analog-to-digital Converter - One Master Clock cycle needed for a transfer from memory to peripheral - Two Master Clock cycles needed for a transfer from peripheral to memory * Next Pointer management for reducing interrupt latency requirement
Low bus arbitration overhead
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The Peripheral DMA Controller handles transfer requests from the channel according to the following priorities (Low to High priorities): Table 7-5. Peripheral DMA Controller
Channel T/R Transmit Transmit Transmit Transmit Transmit Transmit Transmit Transmit Receive Receive Receive Receive Receive Receive Receive Receive Receive
Instance name TWI1 TWI0 PWM UART USART3 USART2 USART1 USART0 TWI0 TWI1 UART USART3 USART2 USART1 USART0 ADC ADC12B
7.8
Debug and Test Features
* Debug access to all memory and registers in the system, including Cortex-M3 register bank when the core is running, halted, or held in reset. * Serial Wire Debug Port (SW-DP) and Serial Wire JTAG Debug Port (SWJ-DP) debug access * Flash Patch and Breakpoint (FPB) unit for implementing break points and code patches * Data Watchpoint and Trace (DWT) unit for implementing watch points, data tracing, and system profiling * Instrumentation Trace Macrocell (ITM) for support of printf style debugging * IEEE(R) 1149.1 JTAG Boundary-scan on all digital pins
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8. Product Mapping
Figure 8-1. SAM3U Memory Mapping
0x00000000 0x00080000 Internal Flash 0 0x00100000 Internal Flash 1 0x00180000 Internal ROM 0x00200000 Reserved 0x1FFFFFFF 0x20000000 1 MByte bit band region 0x20080000 SRAM1 0x20100000 NFC (SRAM) 0x20180000 UDPHS (DMA) 0x20200000 Undefined 0x22000000 0x24000000 0x40000000 32 MBytes bit band alias Undefined 0x400E0000 0x400E0200 MATRIX 0x60000000 0x61000000 Chip Select 1 0x62000000 Chip Select 2 0x63000000 Chip Select 3 0x64000000 reserved 0x68000000 NFC 0x69000000 reserved 0x9FFFFFFF offset block peripheral External SRAM Chip Select 0 0x400E0400 PMC 0x400E0600 UART 0x400E0740 CHIPID 0x400E0800 EFC0 0x400E0A00 EFC1 0x400E0C00 PIOA 0x400E0E00 PIOB 0x400E1000 PIOC 0x400E1200 RSTC ID +0x10 SUPC +0x30 RTT +0x50 WDT +0x60 RTC +0x90 0x400E1400 reserved 0x4007FFFF SYSC GPBR 3 4 2 6 7 10 11 12 1 0x400B0000 DMAC 0x400B3FFF Reserved 0x400E0000 System Controller 0x400E2600 Reserved 0x40100000 Reserved 0x42000000 0x44000000 0x60000000 32 MBytes bit band alias Reserved 5 8 0x400A4000 UDPHS 0x400A8000 ADC12B 0x400AC000 ADC 29 26 27 28 System Controller SMC 0x400A0000 Reserved 0x4009C000 USART3 0xFFFFFFFF System 0x40094000 USART1 0x40098000 USART2 0xE0000000 0x40090000 USART0 Reserved 0x4008C000 PWM 0xA0000000 0x40088000 TWI1 Internal SRAM SRAM0 External SRAM 0x40084000 TWI0 0x60000000 Peripherals +0x40 +0x80 0x40000000 0x40080000 TC0 TC0 TC0 Internal SRAM 0x4000C000 Reserved TC0 TC1 TC2 0x20000000 0x40008000 SPI Code Boot Memory Code 0x40004000 SSC 0x00000000 Address memory space 0x40000000 Peripherals MCI 17 21 20
22 23 24 18 19 25 13 14 15 16 1 MByte bit band region
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9. Memories
The embedded and external memories are described below.
9.1
9.1.1
Embedded Memories
Internal SRAM The SAM3U4 (256-KBytes internal Flash version) embeds a total of 48-Kbytes high-speed SRAM (32-Kbytes SRAM0 and 16-Kbytes SRAM1). The SAM3U2 (128-KBytes internal Flash version) embeds a total of 32-Kbytes high-speed SRAM (16-Kbytes SRAM0 and 16-Kbytes SRAM1). The SAM3U1 (64-KBytes internal Flash version) embeds a total of 16-Kbytes high-speed SRAM (8-Kbytes SRAM0 and 8-Kbytes SRAM1). The SRAM0 is accessible over System Cortex-M3 bus at address 0x2000 0000 and SRAM1 at address 0x2008 0000. The user can see the SRAM as contiguous. The SRAM0 and SRAM1 are in the bit band region. The bit band alias region is from 0x2200 0000 and 0x23FF FFFF. The NAND Flash Controller embeds 4224 bytes of internal SRAM. If the NAND Flash controller is not used, these 4224 Kbytes of SRAM can be used as general purpose. It can be seen at address 0x2010 0000.
9.1.2
Internal ROM The SAM3U product embeds an Internal ROM, which contains the SAM-BA Boot and FFPI program. At any time, the ROM is mapped at address 0x0018 0000.
9.1.3 9.1.3.1
Embedded Flash Flash Overview The Flash of the SAM3U4 (256-KBytes internal Flash version) is organized in two banks of 512 pages (dual plane) of 256 bytes. The Flash of the SAM3U2 (128-KBytes internal Flash version) is organized in one bank of 512 pages (single plane) of 256 bytes. The Flash of the is SAM3U1 (256-KBytes internal Flash version) organized in one bank of 256 pages (single plane) of 256 bytes. The Flash contains a 128-byte write buffer, accessible through a 32-bit interface.
9.1.3.2
Flash Power Supply The Flash is supplied by VDDCORE. Enhanced Embedded Flash Controller The Enhanced Embedded Flash Controller (EEFC) manages accesses performed by the masters of the system. It enables reading the Flash and writing the write buffer. It also contains a User Interface, mapped within the Memory Controller on the APB. The Enhanced Embedded Flash Controller ensures the interface of the Flash block with the 32bit internal bus. Its 128-bit wide memory interface increases performance. 31
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The user can choose between high performance or lower current consumption by selecting either 128-bit or 64-bit access. It also manages the programming, erasing, locking and unlocking sequences of the Flash using a full set of commands. One of the commands returns the embedded Flash descriptor definition that informs the system about the Flash organization, thus making the software generic. The SAM3U4 (256-KBytes internal Flash version) embeds two EEFC (EEFC0 for Flash0 and EEFC1 for Flash1) whereas the SAM3U2/1 embeds one EEFC. 9.1.3.4 Lock Regions In the SAM3U4 (256 KBytes internal Flash version) two Enhanced Embedded Flash Controllers each manage 16 lock bits to protect 32 regions of the flash against inadvertent flash erasing or programming commands. The SAM3U4 (256 KBytes internal Flash version) contains 32 lock regions and each lock region contains 32 pages of 256 bytes. Each lock region has a size of 8 Kbytes. The SAM3U2 (128 KBytes internal Flash version) Enhanced Embedded Flash Controller manages 16 lock bits to protect 32 regions of the flash against inadvertent flash erasing or programming commands. The SAM3U2 (128 KBytes internal Flash version) contains 16 lock regions and each lock region contains 32 pages of 256 bytes. Each lock region has a size of 8 Kbytes. The SAM3U1(64 KBytes internal Flash version) Embedded Flash Controller manages 8 lock bits to protect 8 regions of the flash against inadvertent flash erasing or programming commands. The SAM3U1(64-KBytes internal Flash version) contains 8 lock regions and each lock region contains 32 pages of 256 bytes. Each lock region has a size of 8 Kbytes. If a locked-region's erase or program command occurs, the command is aborted and the EEFC triggers an interrupt. The lock bits are software programmable through the EEFC User Interface. The command "Set Lock Bit" enables the protection. The command "Clear Lock Bit" unlocks the lock region. Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash. 9.1.3.5 Security Bit Feature The SAM3U features a security bit, based on a specific General Purpose NVM bit (GPNVM bit 0). When the security is enabled, any access to the Flash, SRAM, Core Registers and Internal Peripherals either through the ICE interface or through the Fast Flash Programming Interface, is forbidden. This ensures the confidentiality of the code programmed in the Flash. This security bit can only be enabled, through the command "Set General Purpose NVM Bit 0" of the EEFC User Interface. Disabling the security bit can only be achieved by asserting the ERASE pin at 1, and after a full Flash erase is performed. When the security bit is deactivated, all accesses to the Flash, SRAM, Core Registers and Internal Peripherals either through the ICE interface or through the Fast Flash Programming Interface are permitted. It is important to note that the assertion of the ERASE pin should always be longer than 200 ms. As the ERASE pin integrates a permanent pull-down, it can be left unconnected during normal operation. However, it is safer to connect it directly to GND for the final application.
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9.1.3.6 Calibration Bits NVM bits are used to calibrate the brownout detector and the voltage regulator. These bits are factory configured and cannot be changed by the user. The ERASE pin has no effect on the calibration bits. Unique Identifier Each device integrates its own 128-bit unique identifier. These bits are factory configured and cannot be changed by the user. The ERASE pin has no effect on the unique identifier. Fast Flash Programming Interface The Fast Flash Programming Interface allows programming the device through either a serial JTAG interface or through a multiplexed fully-handshaked parallel port. It allows gang programming with market-standard industrial programmers. The FFPI supports read, page program, page erase, full erase, lock, unlock and protect commands. The Fast Flash Programming Interface is enabled and the Fast Programming Mode is entered when TST, NRSTB and FWUP pins are tied high during power up sequence and if all supplies are provided externally (do not use internal regulator for VDDCORE). Please note that since the FFPI is a part of the SAM-BA Boot Application, the device must boot from the ROM. 9.1.3.9 SAM-BA(R) Boot The SAM-BA Boot is a default Boot Program which provides an easy way to program in-situ the on-chip Flash memory. The SAM-BA Boot Assistant supports serial communication via the UART and USB. The SAM-BA Boot provides an interface with SAM-BA Graphic User Interface (GUI). The SAM-BA Boot is in ROM and is mapped in Flash at address 0x0 when GPNVM bit 1 is set to 0. 9.1.3.10 GPNVM Bits The SAM3U features three GPNVM bits that can be cleared or set respectively through the commands "Clear GPNVM Bit" and "Set GPNVM Bit" of the EEFC User Interface. The SAM3U4 is equipped with two EEFC, EEFC0 and EEFC1. EEFC1 does not feature the GPNVM bits. The GPNVM embedded on EEFC0 applies to the two blocks in the SAM3U4. Table 9-1.
GPNVMBit[#] 0 1 2
9.1.3.7
9.1.3.8
General-purpose Non-volatile Memory Bits
Function Security bit Boot mode selection Flash selection (Flash 0 or Flash 1) Only on SAM3U4 (256 Kbytes internal Flash version)
9.1.4
Boot Strategies The system always boots at address 0x0. To ensure a maximum boot possibilities the memory layout can be changed via GPNVM.
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A general purpose NVM (GPNVM1) bit is used to boot either on the ROM (default) or from the Flash. The GPNVM bit can be cleared or set respectively through the commands "Clear General-purpose NVM Bit" and "Set General-purpose NVM Bit" of the EEFC User Interface. Setting the GPNVM Bit 1 selects the boot from the Flash, clearing it selects the boot from the ROM. Asserting ERASE clears the GPNVM Bit 1 and thus selects the boot from the ROM by default. GPNVM2 enables to select if Flash 0 or Flash 1 is used for the boot. Setting the GPNVM2 bit selects the boot from Flash 1, clearing it selects the boot from Flash 0.
9.2
External Memories
The SAM3U offers an interface to a wide range of external memories and to any parallel peripheral.
9.2.1
Static Memory Controller * 8- or 16- bit Data Bus * Up to 24-bit Address Bus (up to 16 MBytes linear per chip select) * Up to 4 chips selects, Configurable Assignment * Multiple Access Modes supported - Byte Write or Byte Select Lines * Multiple device adaptability - Control signals programmable setup, pulse and hold time for each Memory Bank * Multiple Wait State Management - Programmable Wait State Generation - External Wait Request - Programmable Data Float Time * Slow Clock mode supported
9.2.2
NAND Flash Controller * Handles automatic Read/Write transfer through 4224 bytes SRAM buffer * DMA support * Supports SLC NAND Flash technology * Programmable timing on a per chip select basis * Programmable Flash Data width 8-bit or 16-bit
9.2.3
NAND Flash Error Corrected Code Controller * Integrated in the NAND Flash Controller * Single bit error correction and 2-bit Random detection. * Automatic Hamming Code Calculation while writing - ECC value available in a register * Automatic Hamming Code Calculation while reading - Error Report, including error flag, correctable error flag and word address being detected erroneous
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- Supports 8- or 16-bit NAND Flash devices with 512-, 1024-, 2048- or 4096-byte pages
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10. System Controller
The System Controller is a set of peripherals, which allow handling of key elements of the system, such as power, resets, clocks, time, interrupts, watchdog, etc... The System Controller User Interface also embeds the registers used to configure the Matrix. See the system controller block diagram in Figure 10-1 on page 37.
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Figure 10-1. System Controller Block Diagram
VDDBU VDDIN
vr_standby FWUP SHDN Software Controlled Voltage Regulator
VDDOUT
WKUP0 - WKUP15 NRSTB Supply Controller PIOA/B/C Input / Output Buffers VDDIO
PIOx VDDANA
Zero-Power Power-on Reset
General Purpose Backup Registers
ADC (front-end)
ADVREF ADx
SLCK
RTC
rtc_alarm bodbup_in bodbup_on Supply Monitor VDDUTMI
SLCK
RTT
rtt_alarm USB USBx
osc32k_xtal_en vddcore_nreset XIN32 XOUT32 Xtal 32 kHz Oscillator Embedded 32 kHz RC Oscillator XTALSEL Slow Clock SLCK bodcore_on bodcore_in osc32k_rc_en supc_interrupt VDDCORE
Brownout Detector
SRAM
Backup Power Supply
Peripherals vddcore_nreset NRST Reset Controller proc_nreset periph_nreset ice_nreset
Cortex-M3
Matrix Peripheral Bridge
FSTT0 - FSTT15(1)
Embedded 12 / 8 / 4 MHz RC Oscillator
SLCK Main Clock MAINCK
Flash
XIN XOUT
3 - 20 MHz XTAL Oscillator MAINCK PLLA PLLACK
Power Management Controller
Master Clock MCK
SLCK
Watchdog Timer
MAINCK UPLL
UPLLCK
Core Power Supply
FSTT0 - FSTT15 are possible Fast Startup Sources, generated by WKUP0-WKUP15 Pins, but are not physical pins.
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10.1
System Controller and Peripheral Mapping
Please refer to Figure 8-1"SAM3U Memory Mapping" on page 30 . All the peripherals are in the bit band region and are mapped in the bit band alias region.
10.2
Power-on-Reset, Brownout and Supply Monitor
The SAM3U embeds three features to monitor, warn and/or reset the chip: * Power-on-Reset on VDDBU * Brownout Detector on VDDCORE * Supply Monitor on VDDUTMI
10.2.1
Power-on-Reset on VDDBU The Power-on-Reset monitors VDDBU. It is always activated and monitors voltage at start up but also during power down. If VDDBU goes below the threshold voltage, the entire chip is reset. For more information, refer to the Electrical Characteristics section of the datasheet. Brownout Detector on VDDCORE The Brownout Detector monitors VDDCORE. It is active by default. It can be deactivated by software through the Supply Controller (SUPC_MR). It is especially recommended to disable it during low-power modes such as wait or sleep modes. If VDDCORE goes below the threshold voltage, the reset of the core is asserted. For more information, refer to the Supply Controller (SUPC) and Electrical Characteristics sections of the datasheet.
10.2.2
10.2.3
Supply Monitor on VDDUTMI The Supply Monitor monitors VDDUTMI. It is not active by default. It can be activated by software and is fully programmable with 16 steps for the threshold (between 1.9V to 3.4V). It is controlled by the Supply Controller (SUPC). A sample mode is possible. It allows to divide the supply monitor power consumption by a factor of up to 2048. For more information, refer to the SUPC and Electrical Characteristics sections of the datasheet.
10.3
Reset Controller
The Reset Controller is capable to return to the software the source of the last reset, either a general reset, a wake-up reset, a software reset, a user reset or a watchdog reset. The Reset Controller controls the internal resets of the system and the NRST pin output. It is capable to shape a reset signal for the external devices, simplifying to a minimum connection of a push-button on the NRST pin to implement a manual reset.
10.4
Supply Controller
The Supply Controller controls the power supplies of each section of the processor and the peripherals (via Voltage regulator control). The Supply Controller has its own reset circuitry and is clocked by the 32 kHz Slow clock generator. The reset circuitry is based on a zero-power power-on reset cell. The zero-power power-on reset allows the Supply Controller to start properly.
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The Slow Clock generator is based on a 32 kHz crystal oscillator and an embedded 32 kHz RC oscillator. The Slow Clock defaults to the RC oscillator, but the software can enable the crystal oscillator and select it as the Slow Clock source. The Supply Controller starts up the device by enabling the Voltage Regulator, then it generates the proper reset signals to the core power supply. It also enables to set the system in different low power modes and to wake it up from a wide range of events.
10.5
Clock Generator
The Clock Generator is made up of: * One Low Power 32768 Hz Slow Clock Oscillator with bypass mode * One Low Power RC Oscillator * One 3 to 20 MHz Crystal Oscillator, which can be bypassed * One Fast RC Oscillator factory programmed, 3 output frequencies can be selected: 4, 8 or 12 MHz. By default 4 MHz is selected. 8 MHz and 12 MHz output are factory calibrated. * One 480 MHz UPLL providing a clock for the USB High Speed Device Controller. Input frequency is 12 MHz (only). * One 96 to 192 MHz programmable PLL (PLL A), capable to provide the clock MCK to the processor and to the peripherals. The input frequency of the PLL A is between 8 and 16 MHz. Figure 10-2. Clock Generator Block Diagram
Clock Generator XTALSEL
On Chip 32k RC OSC
XIN32 XOUT32
Slow Clock SLCK Slow Clock Oscillator
XIN XOUT
12M Main Oscillator Main Clock MAINCK
On Chip 12/8/4 MHz RC OSC
MAINSEL
PLL B
HSCK
Divider /6 /8
UPLL Clock UPLLCK
PLL and Divider A Status Control
PLLA Clock PLLACK
Power Management Controller
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10.6
Power Management Controller
The Power Management Controller provides all the clock signals to the system. It provides: * the Processor Clock HCLK * the Free running processor clock FCLK * the Cortex SysTick external clock * the Master Clock MCK, in particular to the Matrix and the memory interfaces * the USB Device HS Clock UDPCK * independent peripheral clocks, typically at the frequency of MCK * three programmable clock outputs: PCK0, PCK1 and PCK2 The Supply Controller selects between the 32 kHz RC oscillator or the crystal oscillator. The unused oscillator is disabled automatically so that power consumption is optimized. By default, at startup the chip runs out of the Master Clock using the Fast RC Oscillator running at 4 MHz.
Figure 10-3.
Power Management Controller Block Diagram
Processor Clock Controller Sleep Mode HCK int
Divider /8
SystTick
FCLK Master Clock Controller SLCK MAINCK PLLACK PLLBCK Prescaler /1,/2,/4,...,/64 Peripherals Clock Controller ON/OFF MCK
periph_clk[..]
Programmable Clock Controller SLCK MAINCK PLLACK PLLBCK ON/OFF Prescaler /1,/2,/4,...,/64 pck[..]
USB Clock Controller ON/OFF HSCK UDPCK
The SysTick calibration value is fixed at 10500, which allows the generation of a time base of 1 ms with SystTick clock to 10.5 MHz (max HCLK/8).
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10.7 Watchdog Timer
* 16-bit key-protected once-only Programmable Counter * Windowed, prevents the processor to be in a dead-lock on the watchdog access
10.8
SysTick Timer
* 24-bit down counter * Self-reload capability * Flexible system timer
10.9
Real-time Timer
* Real-time Timer, allowing backup of time with different accuracies - 32-bit Free-running back-up Counter - Integrates a 16-bit programmable prescaler running on slow clock - Alarm Register capable to generate a wake-up of the system
10.10 Real-time Clock
* Low power consumption * Full asynchronous design * Two hundred year calendar * Programmable Periodic Interrupt * Alarm and update parallel load * Control of alarm and update Time/Calendar Data In
10.11 General-Purpose Back-up Registers
* Eight 32-bit general-purpose backup registers
10.12 Nested Vectored Interrupt Controller
* Thirty maskable interrupts * Sixteen priority levels * Dynamic reprioritization of interrupts * Priority grouping - selection of preempting interrupt levels and non preempting interrupt levels. * Support for tail-chaining and late arrival of interrupts. - back-to-back interrupt processing without the overhead of state saving and restoration between interrupts. * Processor state automatically saved on interrupt entry, and restored on - interrupt exit, with no instruction overhead.
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10.13 Chip Identification
* Chip Identifier (CHIPID) registers permit recognition of the device and its revision. Table 10-1. SAM3U Chip IDs Register
Flash Size KByte 256 128 64 256 128 64 Pin Count 100 100 100 144 144 144 CHIPID_CIDR 0x28000960 0x280A0760 0x28090560 0x28100960 0x281A0760 0x28190560 CHIPID_EXID 0x0 0x0 0x0 0x0 0x0 0x0
Chip Name SAM3U4C (Rev A) SAM3U2C (Rev A) SAM3U1C (Rev A) SAM3U4E (Rev A) SAM3U2E (Rev A) SAM3U1E (Rev A)
* JTAG ID: 0x0582A03F
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10.14 PIO Controllers
* 3 PIO Controllers, PIOA, PIOB, and PIOC, controlling a maximum of 96 I/O Lines * Each PIO Controller controls up to 32 programmable I/O Lines - PIOA has 32 I/O Lines - PIOB has 32 I/O Lines - PIOC has 32 I/O Lines * Fully programmable through Set/Clear Registers * Multiplexing of two peripheral functions per I/O Line * For each I/O Line (whether assigned to a peripheral or used as general purpose I/O) - Input change, rising edge, falling edge, low level and level interrupt - Debouncing and Glitch filter - Multi-drive option enables driving in open drain - Programmable pull up on each I/O line - Pin data status register, supplies visibility of the level on the pin at any time * Synchronous output, provides Set and Clear of several I/O lines in a single write
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11. Peripherals
11.1 Peripheral Identifiers
Table 11-1 defines the Peripheral Identifiers of the SAM3U. A peripheral identifier is required for the control of the peripheral interrupt with the Nested Vectored Interrupt Controller and for the control of the peripheral clock with the Power Management Controller. Note that some Peripherals are always clocked. Please refer to the table below. Table 11-1.
Instance ID 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
Peripheral Identifiers
Instance Name SUPC RSTC RTC RTT WDT PMC EEFC0 EEFC1 UART SMC PIOA PIOB PIOC USART0 USART1 USART2 USART3 HSMCI TWI0 TWI1 SPI SSC TC0 TC1 TC2 PWM ADC12B ADC DMAC UDPHS NVIC Interrupt X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X PMC Clock Control Instance Description Supply Controller Reset Controller Real Time Clock Real Time Timer Watchdog Timer Power Management Controller Enhanced Embedded Flash Controller 0 Enhanced Embedded Flash Controller 1 Universal Asynchronous Receiver Transmitter Static Memory Controller Parallel I/O Controller A, Parallel I/O Controller B Parallel I/O Controller C USART 0 USART 1 USART 2 USART 3 High Speed Multimedia Card Interface Two-Wire Interface 0 Two-Wire Interface 1 Serial Peripheral Interface Synchronous Serial Controller Timer Counter 0 Timer Counter 1 Timer Counter 2 Pulse Width Modulation Controller 12-bit ADC Controller 10-bit ADC Controller DMA Controller USB Device High Speed
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11.2 Peripheral Signal Multiplexing on I/O Lines
The SAM3U features 3 PIO controllers, PIOA, PIOB and PIOC that multiplex the I/O lines of the peripheral set. Each PIO Controller controls up to 32 lines. Each line can be assigned to one of two peripheral functions, A or B. The multiplexing tables in the following pages define how the I/O lines of peripherals A and B are multiplexed on the PIO Controllers. The two columns "Extra Function" and "Comments" have been inserted in this table for the user's own comments, they may be used to track how pins are defined in an application. Note that some peripheral functions which are output only, might be duplicated within the tables.
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11.2.1
PIO Controller A Multiplexing Multiplexing on PIO Controller A (PIOA)
Peripheral A TIOB0 TIOA0 TCLK0 MCCK MCCDA MCDA0 MCDA1 MCDA2 MCDA3 TWD0 TWCK0 URXD UTXD MISO MOSI SPCK NPCS0 SCK0 TXD0 RXD0 TXD1 RXD1 TXD2 RXD2 TWD1 TWCK1 TD RD TK RK TF RF PWMH2 NCS1 ADTRG PWMFI2 NPCS3 PWMH3 PCK0 RTS1 CTS1 SCK1 SCK2 TCLK2 PCK0 PWMH0 PWMH1 TIOA2 TIOB2 AD12B1 WKUP11(1)(2) WKUP12(1)(2) WKUP5(1)(2) WKUP6(1)(2) WKUP7(1)(2) WKUP8(1)(2) WKUP9(1)(2) WKUP10(1)(2) AD12B0 Peripheral B NPCS1 NPCS2 AD12BTRG PCK1 PWMH0 PWMH1 PWMH2 PWML0 PWML1 PWML2 PWML3 PWMFI0 PWMFI1 WKUP3(1)(2) WKUP4(1)(2) Extra Function WKUP0
(1)(2)
Table 11-2.
I/O Line PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31 Notes:
Comments
WKUP1(1)(2) WKUP2(1)(2)
1. Wake-Up source in Backup mode (managed by the SUPC). 2. Fast Start-Up source in Wait mode (managed by the PMC).
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11.2.2 PIO Controller B Multiplexing Multiplexing on PIO Controller B (PIOB)
Peripheral A PWMH0 PWMH1 PWMH2 PWMH3 TCLK1 TIOA1 TIOB1 RTS0 CTS0 D0 D1 D2 D3 D4 D5 D6 D7 NANDOE NANDWE NRD NCS0 A21/NANDALE A22/NANDCLE NWR0/NWE NANDRDY D8 D9 D10 D11 D12 D13 D14 Peripheral B A2 A3 A4 A5 A6 A7 D15 A0/NBS0 A1 DTR0 DSR0 DCD0 RI0 PWMH0 PWMH1 PWMH2 PWMH3 PWML0 PWML1 PWML2 PWML3 RTS2 CTS2 PCK2 PCK1 PWML0 PWML1 PWML2 PWML3 Only on 144-pin version Only on 144-pin version Only on 144-pin version Only on 144-pin version Only on 144-pin version Only on 144-pin version Only on 144-pin version Extra Function WKUP13
(1)(2)
Table 11-3.
I/O Line PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 PB15 PB16 PB17 PB18 PB19 PB20 PB21 PB22 PB23 PB24 PB25 PB26 PB27 PB28 PB29 PB30 PB31 Notes:
Comments
WKUP14(1)(2) WKUP15(1)(2) AD12B2 AD12B3 AD0 AD1 AD2 AD3
1. Wake-Up source in Backup mode (managed by the SUPC). 2. Fast Start-Up source in Wait mode (managed by the PMC).
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11.2.3
PIO Controller C Multiplexing Multiplexing on PIO Controller C (PIOC)
Peripheral A A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 NCS1 A2 A3 NWR1/NBS1 NCS2 NCS3 NWAIT SCK3 A14 A15 A16 A17 A18 A19 A20 A23 PWMH0 PWMH1 PWMH2 PWMH3 MCDA4 PWML0 PWML1 PWML2 MCDA5 MCDA6 MCDA7 AD4 AD5 AD6 AD7 NPCS1 PWML3 NPCS1 NPCS2 NPCS3 PWML0 PWML1 PWML2 PWML3 CTS3 RTS3 TXD3 RXD3 NPCS2 AD12B4 AD12B5 AD12B6 AD12B7 Peripheral B Extra function Comments Only on 144-pin version Only on 144-pin version Only on 144-pin version Only on 144-pin version Only on 144-pin version Only on 144-pin version Only on 144-pin version Only on 144-pin version Only on 144-pin version Only on 144-pin version Only on 144-pin version Only on 144-pin version Only on 144-pin version Only on 144-pin version Only on 144-pin version Only on 144-pin version Only on 144-pin version Only on 144-pin version Only on 144-pin version Only on 144-pin version Only on 144-pin version Only on 144-pin version Only on 144-pin version Only on 144-pin version Only on 144-pin version Only on 144-pin version Only on 144-pin version Only on 144-pin version Only on 144-pin version Only on 144-pin version Only on 144-pin version Only on 144-pin version
Table 11-4.
I/O Line PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15 PC16 PC17 PC18 PC19 PC20 PC21 PC22 PC23 PC24 PC25 PC26 PC27 PC28 PC29 PC30 PC31 Notes:
1. Wake-Up source in Backup mode (managed by the SUPC). 2. Fast Start-Up source in Wait mode (managed by the PMC).
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12. Embedded Peripherals Overview
12.1 Serial Peripheral Interface (SPI)
* Supports communication with serial external devices - Four chip selects with external decoder support allow communication with up to 15 peripherals - Serial memories, such as DataFlash and 3-wire EEPROMs - Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and Sensors - External co-processors * Master or slave serial peripheral bus interface - 8- to 16-bit programmable data length per chip select - Programmable phase and polarity per chip select - Programmable transfer delays between consecutive transfers and between clock and data per chip select - Programmable delay between consecutive transfers - Selectable mode fault detection * Very fast transfers supported - Transfers with baud rates up to MCK - The chip select line may be left active to speed up transfers on the same device
12.2
Two Wire Interface (TWI)
* Master, Multi-Master and Slave Mode Operation * Compatibility with Atmel two-wire interface, serial memory and I2C compatible devices * One, two or three bytes for slave address * Sequential read/write operations * Bit Rate: Up to 400 kbit/s * General Call Supported in Slave Mode * Connecting to PDC channel capabilities optimizes data transfers in Master Mode only - One channel for the receiver, one channel for the transmitter - Next buffer support
12.3
Universal Asynchronous Receiver Transceiver (UART)
* Two-pin UART - Implemented features are 100% compatible with the standard Atmel USART - Independent receiver and transmitter with a common programmable Baud Rate Generator - Even, Odd, Mark or Space Parity Generation - Parity, Framing and Overrun Error Detection - Automatic Echo, Local Loopback and Remote Loopback Channel Modes - Support for two PDC channels with connection to receiver and transmitter
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12.4
Universal Synchronous Asynchronous Receiver Transmitter (USART)
* Programmable Baud Rate Generator * 5- to 9-bit full-duplex synchronous or asynchronous serial communications - 1, 1.5 or 2 stop bits in Asynchronous Mode or 1 or 2 stop bits in Synchronous Mode - Parity generation and error detection - Framing error detection, overrun error detection - MSB- or LSB-first - Optional break generation and detection - By 8 or by-16 over-sampling receiver frequency - Hardware handshaking RTS-CTS - Receiver time-out and transmitter timeguard - Optional Multi-drop Mode with address generation and detection - Optional Manchester Encoding * RS485 with driver control signal * ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards - NACK handling, error counter with repetition and iteration limit * SPI Mode - Master or Slave - Serial Clock programmable Phase and Polarity - SPI Serial Clock (SCK) Frequency up to MCK/4 * IrDA modulation and demodulation - Communication at up to 115.2 Kbps * Test Modes - Remote Loopback, Local Loopback, Automatic Echo
12.5
Serial Synchronous Controller (SSC)
* Provides serial synchronous communication links used in audio and telecom applications (with CODECs in Master or Slave Modes, I2S, TDM Buses, Magnetic Card Reader, ...) * Contains an independent receiver and transmitter and a common clock divider * Offers a configurable frame sync and data length * Receiver and transmitter can be programmed to start automatically or on detection of different event on the frame sync signal * Receiver and transmitter include a data signal, a clock signal and a frame synchronization signal
12.6
Timer Counter (TC)
* Three 16-bit Timer Counter Channels * Wide range of functions including: - Frequency Measurement - Event Counting - Interval Measurement
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- Pulse Generation - Delay Timing - Pulse Width Modulation - Up/Down Capabilities - Quadrature Decoder Logic * Each channel is user-configurable and contains: - Three external clock inputs - Five internal clock inputs - Two multi-purpose input/output signals * Two global registers that act on all three TC Channels
12.7
Pulse Width Modulation Controller (PWM)
* 4 channels, one 16-bit counter per channel * Common clock generator, providing Thirteen Different Clocks - A Modulo n counter providing eleven clocks - Two independent Linear Dividers working on modulo n counter outputs - High Frequency Asynchronous clocking mode * Independent channel programming - Independent Enable Disable Commands - Independent Clock Selection - Independent Period and Duty Cycle, with Double Buffering - Programmable selection of the output waveform polarity - Programmable center or left aligned output waveform - Independent Output Override for each channel - Independent complementary Outputs with 12-bit dead time generator for each channel - Independent Enable Disable Commands - Independent Clock Selection - Independent Period and Duty Cycle, with Double Buffering * Synchronous Channel mode - Synchronous Channels share the same counter - Mode to update the synchronous channels registers after a programmable number of periods * Connection to one PDC channel - Offers Buffer transfer without Processor Intervention, to update duty cycle of synchronous channels * Two independent event lines which can send up to 8 triggers on ADC within a period * Four programmable Fault Inputs providing asynchronous protection of outputs
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12.8
High Speed Multimedia Card Interface (HSMCI)
* Compatibility with MultiMedia Card Specification Version 4.3 * Compatibility with SD Memory Card Specification Version 2.0 * Compatibility with SDIO Specification Version V2.0. * Compatibility with CE-ATA Specification 1.1 * Cards clock rate up to Master Clock divided by 2 * Boot Operation Mode support * High Speed mode support * Embedded power management to slow down clock rate when not used * HSMCI has one slot supporting - One MultiMediaCard bus (up to 30 cards) or - One SD Memory Card - One SDIO Card * Support for stream, block and multi-block data read and write * Supports Connection to DMA controller - Minimizes Processor intervention for large buffer transfers * Built in FIFO (32 bytes) with large Memory Aperture Supporting Incremental access * Support for CE-ATA Completion Signal Disable Command
12.9
USB High Speed Device Port (UDPHS)
* USB V2.0 high-speed compliant, 480 MBits per second * Embedded USB V2.0 UTMI+ high-speed transceiver * Embedded 4-Kbyte dual-port RAM for endpoints * Embedded 6 channels DMA controller * Suspend/Resume logic * Up to 2 or 3 banks for isochronous and bulk endpoints * Seven endpoints, configurable by software * Maximum configuration: seven endpoints: - Endpoint 0: 64 bytes, 1 bank mode - Endpoint 1 & 2: 512 bytes, 2 banks mode, HS isochronous capable - Endpoint 3 & 4:64 bytes, 3 banks mode - Endpoint 5 & 6: 1024 bytes, 3 banks mode, HS isochronous capable
12.10 Analog-to-Digital Converter (ADC)
Two ADCs are embedded in the product. 12.10.1 12-bit High Speed ADC * 8-channel ADC * 12-bit 1 Msamples/sec. Cyclic Pipeline ADC * Integrated 8-to-1 multiplexer * 12-bit resolution
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* Selectable single ended or differential input voltage * Programmable gain for maximum full scale input range * External voltage reference for better accuracy on low voltage inputs * Individual enable and disable of each channel * Multiple trigger sources - Hardware or software trigger - External trigger pin - Timer Counter 0 to 2 outputs TIOA0 to TIOA2 trigger - PWM trigger * Sleep Mode and conversion sequencer - Automatic wakeup on trigger and back to sleep mode after conversions of all enabled channels 12.10.2 10-bit Low Power ADC * 8-channel ADC * 10-bit 384 Ksamples/sec. or 8-bit 533 Ksamples/sec. Successive Approximation Register ADC * -2/+2 LSB Integral Non Linearity, -1/+1 LSB Differential Non Linearity * Integrated 8-to-1 multiplexer * External voltage reference for better accuracy on low voltage inputs * Individual enable and disable of each channel * Multiple trigger sources - Hardware or software trigger - External trigger pin - Timer Counter 0 to 2 outputs TIOA0 to TIOA2 trigger - PWM trigger * Sleep Mode and conversion sequencer - Automatic wakeup on trigger and back to sleep mode after conversions of all enabled channels
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13. Package Drawings
Figure 13-1. 100-ball LQFP Package Mechanical Drawing
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Figure 13-2. 100-ball LFBGA Package Mechanical Drawing
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Figure 13-3. 144-lead LQFP Package Mechanical Drawing
Notes:
1. This drawing is for general information only; refer to JEDEe Drawing MS-026 for additional information. 2. The top package body size may be smaller than the bottom package size by as much as 0.15 mm. 3. Dimensions D1 and E1 do not include mold protrusions. Allowable protrusion is 0.25 mm per side. D1 and E1 are maximum plastic body size dimensions including mold mismatch. 4. b dimension by more than 0.08 mm. Dambar cannot be located on the lower radius or the foot. Minimum space between protrusion and an adjacent lead is 0.07 mm for 0.4 and 0.5 mm pitch packages. 5. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip. 6. A1 is defined as the distance from the seating place to the lowest point on the package body.
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Figure 13-4. 144-ball LFBGA Mechanical Drawing
All dimensions are in mm.
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14. Ordering Information
Table 14-1. ATSAM3U4/2/1 Ordering Information
MRL A A A A A A A A A A A A Flash (Kbytes) 256 256 256 256 128 128 128 128 64 64 64 64 Package LQFP144 LFBGA 144 LQFP 100 TFBGA100 LQFP144 LFBGA144 LQFP100 TFBGA100 LQFP144 LFBGA144 LQFP100 TFBGA100 Package Type Green Green Green Green Green Green Green Green Green Green Green Green Temperature Operating Range Industrial -40C to 85C Industrial -40C to 85C Industrial -40C to 85C Industrial -40C to 85C Industrial -40C to 85C Industrial -40C to 85C Industrial -40C to 85C Industrial -40C to 85C Industrial -40C to 85C Industrial -40C to 85C Industrial -40C to 85C Industrial -40C to 85C
Ordering Code ATSAM3U4EA-AU ATSAM3U4EA-CU ATSAM3U4CA-AU ATSAM3U4CA-CU ATSAM3U2EA-AU ATSAM3U2EA-CU ATSAM3U2CA-AU ATSAM3U2CA-CU ATSAM3U1EA-AU ATSAM3U1EA-CU ATSAM3U1CA-AU ATSAM3U1CA-CU
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Revision History
In the tables that follow, the most recent version of the document appears first.
"rfo" indicates changes requested during the review and approval loop. Change Request Ref.
Doc Rev 6430B
Comments
Introduction: Section 1. "SAM3U Description", Updated: 52 Kbytes of SRAM. 4x USARTs (SAM3U1C/2C/4C have 3), up to 6400 2x TWIs (SAM3U1C/2C/4C have 1), up to 5x SPIs SAM3U1C/2C/4C have 4), Table 1-1, "Configuration Summary",EBI column updated, 8 bits for SAM3U1C/2C/4C SAM3U4/3/2C rows FWUP replaces NO in FWUP,SHDN pins column 6642 Figure 2-1 "144-pin SAM3U4/2/1E Block Diagram" and Figure 2-2 "100-pin SAM3U4/2/1C Block Diagram" updated, SM cell removed; UART moved to peripheral area, added Flash Unique block, removed 12B from ADC block, added SysTick counter and Fmax 96 MHz to M3 block. FWUP replaces WKUP in fig 2-1, FWUP added to fig 2-2 Figure 2-2 "100-pin SAM3U4/2/1C Block Diagram", NWR1/NBS1, NXRP0, A0 removed from block diagram. Table 3-1, "Signal Description List", Schmitt Trigger added "PIO Controller - PIOA - PIOB - PIOC". exception details given in footnote. VDDIN, VDDOUT added to table. "Serial Wire/JTAG Debug Port (SWJ-DP)" replaced ICE and JTAG. This section of the table updated status of pulldowns and pullups specified. Section 4. "Package and Pinout", reorganized according to product. Section 4.1 "SAM3U4/2/1E Package and Pinout" and Section 4.2 "SAM3U4/2/1C Package and Pinout", pinouts finalized in datasheet. Section 5.5.1 "Backup Mode", BOD replaced by Supply Monitor/SM. FWUP Falling Edge Detector. Figure 5-4 "Wake-up Source", BODEN replaced by SMEN. Table 5-1, "Low Power Mode Configuration Summary", PIO state in Low Power Modes, backup mode is; "Previous state saved. Section 6.6 "NRSTB Pin", VDDIO changed to VDDBU Section 6. "Input/Output Lines", replaces Section 5.8 "Programmable I/O Lines". Section 6.1 "General Purpose I/O Lines (GPIO)" and Section 6.2 "System I/O Lines", replace Section 6. "I/O Line Considerations". Figure 6-1 "On-Die Termination schematic", added. Section 6.8 "PIO Controllers", removed. Section 8. "Product Mapping", title changed from "Memories". Section 9. "Memories", now comprises Section 9.1 "Embedded Memories" and Section 9.2 "External Memories". Section 9.1.3.5 "Security Bit Feature", updated Table 7-3, "SAM3U Master to Slave Access", Slave 9, High Speed Peripheral Bridge line added. Section 7.2 "APB/AHB Bridges", reference to ADC updated "10-bit ADC, 12-bit ADC (ADC12B)". Table 11-3, "Multiplexing on PIO Controller B (PIOB)", ADC12B2, ADC12B3 properly listed. Section 12.10.1 "12-bit High Speed ADC", Section 12.10.2 "10-bit Low Power ADC", titles changed. "Quadrature Decoder Logic" on page 51, properly stated in list of TC functions. Section 12.10.1 "12-bit High Speed ADC", 2nd item on list updated. Section 12.10.2 "10-bit Low Power ADC", Ksample values updated on 2nd item of list. 6482/6642
rfo 6480 rfo
6471/rfo 6607 rfo 6645 6646 6481/rfo
6663 6397
rfo
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Doc. Rev 6430AS
Comments First issue
Change Request Ref.
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6430BS-ATARM-01-Sep-09

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